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1 ut54acs164245sei schmitt cmos 16-bit bidirectio nal multipurpose transceiver datasheet july, 2010 www.aeroflex.com/16bitlogic features ? flexible voltage operation - 5v bus to 3.3v bus; 5v bus to 5v bus - 3.3v bus to 5v bus; 3.3v bus to 3.3v bus ? cold sparing - 1m minimum input impedance power-off ? warm sparing - guaranteed output tri-state wh ile one power supply is "off" and the other is "on" - 1m minimum input impedance power-off ? 0.6 m crh cmos technology ? operational environment: - total dose: 100 krads(si) - single event latchup immune ? high speed, low power consumption ? schmitt trigger inputs to filter noisy signals ? available qml q or v processes ? standard microcircuit drawing 5962-98580 - device types 06 and 07 ? package: - 48-lead flatpack, 25 mil pitch (.390 x .640), wgt 1.4 grams description the 16-bit wide ut54acs164245sei multipurpose transceiv- er is built using aeroflex?s crh technology. this high speed, low power ut54acs164245sei transceiver is designed to per- form multiple functions including: asynchronous two-way communication, schmitt input buffering, voltage translation, cold and warm sparing. with either or both v dd1 and v dd2 are equal to zero volts, the ut54acs164245sei outputs and inputs present a minimum impedance of 1m making it ideal for "cold spare" applications. balanced outputs and low "on" output im- pedance make the ut54acs164245sei well suited for driving high capacitance loads and lo w impedance backplanes. the ut54acs164245sei enables system designers to interface 3.3 volt cmos compatible components with 5 volt cmos compo- nents. for voltage translation, th e a port interfaces with the 3.3 volt bus; the b port interfaces with the 5 volt bus. the direction control (dirx) controls the direction of data flow. the output enable (oe x) overrides the direction control and disables both ports. these signals can be driven from either port a or b. the direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit trans- ceiver. logic symbol (48) oe 1 g2 (47) 1a1 (46) 1a2 (44) (2) 1b1 (5) (3) 1b2 1a3 (43) 1a4 (41) 1a5 (40) 1a6 1b3 (9) 1b6 (8) 1b5 (6) 1b4 (38) 1a7 (37) 1a8 (12) 1b8 (11) 1b7 (1) dir1 1en1 (ba) 1en2 (ab) 11 12 (25) oe 2 g1 (24) dir2 21 22 (36) 2a1 2b1 (13) (35) 2a2 (33) 2a3 (32) 2a4 (30) 2a5 (29) 2a6 (27) 2a7 (26) 2a8 (16) 2b2 2b3 (20) 2b6 (19) 2b5 (17) 2b4 (23) 2b8 (22) 2b7 (14) 2en1 (ba) 2en2 (ab)
2 pin description function table pinouts pin names description oe x output enable input (active low) dirx direction control inputs xax side a inputs or 3-state outputs (3.3v port) xbx side b inputs or 3-state outputs (5v port) enable oe x direction dirx operation l l b data to a bus l h a data to b bus h x isolation 1 2 3 4 5 7 6 48 47 46 45 44 42 43 dir1 1b1 1b2 v ss 1b3 1b4 vdd1 oe 1 1a1 1a2 v ss 1a3 vdd2 8 41 1b5 1a5 1a4 9 40 1b6 1a6 10 39 v ss v ss 48-lead flatpack top view 1b7 1b8 2b1 2b2 v ss 2b3 2b4 vdd1 2b5 2b6 11 12 13 14 15 17 16 18 19 20 v ss 2b7 2b8 dir2 21 22 23 24 38 37 36 35 34 32 33 1a7 1a8 2a1 2a2 v ss 2a4 31 vdd2 2a3 30 2a5 29 2a6 28 v ss 27 2a7 26 2a8 25 oe 2
3 io guidelines all inputs are 5 volt tolerant. wh en vdd2 is at 3.3 volts, either 3.3 or 5 volt cmos logic levels can be applied to all control in- puts. it is recommended that all unused inputs be tied to vss through a 1k to 10k resistor. it's good design practice to tie the unused input to vss via a re- sistor to reduce noise susceptibili ty. the resistor protects the in- put pin by limiting the current from high going variations in vss. the number of inputs that can be tied to the resistor pull-down can vary. it is up to the system designer to choose how many inputs are tied together by figuring out the max load the part can drivewhile still meeting system performance specs. input signal transitions should be driven to the device with a rise and fall time that is <100ms. power table power application guidelines for proper operation, connect power to all v dd pins and ground all v ss pins (i.e., no floating v dd or v ss input pins). by virtue of the ut54acs164245sei warm spare feature, power supplies v dd1 and v dd2 may be applied to the device in any order. to ensure the device is in cold spare mode, both supplies, v dd1 and v dd2 must be equal to v ss +/- 0.3v. warm sp are operation is in effect when one power supply is >1v and the other power supply is equal to v ss +/- 0.3v. if v dd1 has a power on ramp longer than 1 second, then v dd2 should be powered on first to ensure proper control of dirx and oe x. during normal opera- tion of the part, after power-up, ensure vdd1> vdd2. by definition, warm sparing occu rs when half of the chip re- ceives its normal v dd supply value while the v dd supplying the other half of the chip is set to 0.0v. when the chip is "warm spared", the side that has v dd set to a normal operational value is "actively" tri-stated because th e chip?s internal oe signal is forced low. the side of the chip that has v dd set to 0.0v is "pas- sively" tri-stated by the cold spar e circuitry. in order to mini- mize transients and current consum ption, the user is encouraged to first apply a high level to the oe x pins and then power down the appropriate supply. port b port a operation 5 volts 3.3 volts voltage translator 5 volts 5 volts non translating 3.3 volts 3.3 volts non translating v ss v ss cold spare v ss 3.3v or 5v port a warm spare 3.3v or 5v v ss port b warm spare
4 logic diagram 1a1 1a2 1a3 1a4 1a5 1a6 1a7 1a8 dir1 (1) (47) (48) (2) (46) (3) (44) (5) (43) (6) (41) (8) (40) (9) (38) (11) (37) (12) 1b1 1b2 1b3 1b6 1b5 1b4 1b8 1b7 oe 1 2a1 2a2 2a3 2a4 2a5 2a6 2a7 2a8 dir2 (24) (36) (25) (13) (35) (14) (33) (16) (32) (17) (30) (19) (29) (20) (27) (22) (26) (23) 2b1 2b2 2b3 2b6 2b5 2b4 2b8 2b7 oe 2 3.3v port 5 v port 3.3v port 5 v port
5 operational environment 1 notes: 1. logic will not latchup during radiation expo sure within the limits defined in the table. 2. not tested, inherent of cmos technology. absolute maximum ratings 1 note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability and performance. 2. for cold spare mode (v dd = v ss ), v i/o may be -0.3v to the maximum recommended operating v dd + 0.3v. dual supply operating conditions parameter limit units total dose 1.0e5 rad(si) sel immune >114 mev-cm 2 /mg neutron fluence 2 1.0e14 n/cm 2 symbol parameter limit (mil only) units v i/o (port b) 2 voltage any pin during operation -.3 to v dd1 +.3 v v i/o (port a) 2 voltage any pin during operation -.3 to v dd1 +.3 v v dd1 supply voltage -0.3 to 6.0 v v dd2 supply voltage -0.3 to 6.0 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd1 supply voltage 3.0 to 3.6 or 4.5 to 5.5 v v dd2 supply voltage 3.0 to 3.6 or 4.5 to 5.5 v v in (port b) input voltage any pin 0 to v dd1 v v in (port a) input voltage any pin 0 to v dd2 v t c temperature range -55 to + 125 c
6 dc electrical characteristics 1 (tc = -55 c to +125 c for "c" screening and -40 c to +125 c for "w" screening) symbol parameter condition min max unit v t + schmitt trigger, positive going threshold 2 v dd from 3.0 to 5.5 .7v dd v v t - schmitt trigger, negative going threshold 2 v dd from 3.0 to 5.5 .3v dd v v h1 schmitt trigger range of hysteresis v dd from 4.5 to 5.5 0.6 v v h2 schmitt trigger range of hysteresis v dd from 3.0 to 3.6 0.4 v i in input leakage current v dd from 3.6 to 5.5 v in = v dd or v ss -1 3 a i oz three-state output leakage current v dd from 3.6 to 5.5 v in = v dd or v ss -1 3 a i cs cold sparing leakage current 3 v in = 5.5 v dd = v ss -1 5 a i ws warm sparing input leakage current (any pin) 3 v in = 5.5v v dd1 = v ss & v dd2 = 3.0v to 5.5v or v dd1 = 3.0v to 5.5v & v dd2 = v ss -1 5 a i os1 short-circuit output current 6, 10 v o = v dd or v ss v dd from 4.5 to 5.5 -200 200 ma i os2 short-circuit output current 6, 10 v o = v dd or v ss v dd from 3.0 to 3.6 -100 100 ma v ol1 low-level output voltage 4 i ol = 8ma i ol = 100 a v dd = 4.5 0.4 0.2 v v ol2 low-level output voltage 4 i ol = 8ma i ol = 100 a v dd = 3.0 0.5 0.2 v v oh1 high-level output voltage 4 i oh = -8ma i oh = -100 a v dd = 4.5 v dd - 0.7 v dd - 0.2 v v oh2 high-level output voltage 4 i oh = -8ma i oh = -100 a v dd = 3.0 v dd - 0.9 v dd - 0.2 v
7 notes: 1. all specifications va lid for radiation dose 1e5 rad(si) per mil-std-883, method 1019. 2. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 3. this parameter is unaffected by the state of oe x or dirx. 4. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per outp ut buffer) times frequency should not exceed 3,765 pf-mhz. 5. guaranteed by characterization. 6. not more than one output may be shorted at a time for maximum duration of one second. 7. power does not include power contribution of any cmos output sink current. 8. power dissipation specified per switching output. 9.capacitance measured for initial qualificatio n and when design changes ma y affect the value. capac itance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 10. supplied as a design limit, but not guaranteed or tested. . p total1 power dissipation 5,7, 8 c l = 50pf v dd from 4.5 to 5.5 2.0 mw/ mhz p total2 power dissipation 5, 7, 8 c l = 50pf v dd from 3.00 to 3.6 1.5 mw/ mhz i ddq standby supply current v dd1 or v dd2 pre-rad 25 o c pre-rad -55 o c to +125 o c post-rad 25 o c v in = v dd or v ss v dd = 5.5 oe = v dd oe = v dd oe = v dd 60 100 100 a a a c in input capacitance 9 ? = 1mhz @ 0v v dd from 3.0 to 5.5 15 pf c out output capacitance 9 ? = 1mhz @ 0v v dd from 3.0 to 5.5 15 pf
8 ac electrical characteristics* 1 (port b = 5 volt, port a = 3.3 volt) (v dd1 = 5v 10%; v dd2 = 3.3v 0.3v ) (tc = -55 c to +125 c for "c" screening and -40 c to +125 c for "w" screening) notes: * for devices procured with a total ionizing dose tolerance gu arantee, the post-irradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. all specifications va lid for radiation dose 1e5 rad(si) per mil-std-883, method 1019. 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested 3. output skew is defined as a comparison of any two output tr ansitions of the same type at th e saame temperature and voltage f or the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus high-to-low an d low-to-high versus low-to-high; similarly 1b1 through 1b8 are compared, 2a1 through 2a8 are compared, and 2b1 through 2b8 are compared. 4. differential output skew is defined as a comparison of any two outp ut transitions of opposite ty pes on the same type at the same temperature and voltage for the same port within the same byte: 1a1 through 1a8 are compared high-t o-low versus low-to-high; simila rly 1b1 through 1b8 are compared , 2a1 through 2a8 are compared, and 2b1 through 2b8 are compared. . symbol parameter min max unit ut54acs164245sei t plh propagation delay data to bus 3.5 11 ns t phl propagation delay data to bus 3.5 11 ns t pzl output enable time oe x to bus 2.5 16 ns t pzh output enable time oe x to bus 2.5 16 ns t plz output disable time oe x to bus high impedance 2.5 16 ns t phz output disable time oe x to bus high impedance 2.5 16 ns t pzl 2 output enable time dirx to bus 1 18 ns t pzh 2 output enable time dirx to bus 1 18 ns t plz 2 output disable time dirx to bus high impedance 1 20 ns t phz 2 output disable time dirx to bus high impedance 1 20 ns t skew 3 skew between outputs - 600 ps t dskew 4 differential skew between outputs - 1.5 ns
9 t plz t pzh t pzl t phl t phz propagation delay input output v dd v dd /2 0v t plh v oh v ol v dd /2 control input 5v output normally low enable disable times 5v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8v dd .2v dd v dd /2+0.2 v dd /2-0.2 .2v dd + .2v .8v dd - .2v t plz t pzh t pzl t phz 3.3v output normally low 3.3v output normally high v dd /2 v dd /2 .7v dd .2v dd v dd /2+0.2 v dd /2-0.2 .2v dd + .2v .7v dd - .2v
10 ac electrical characteristics* 1 (port a = port b, 5 volt operation) (v dd1 = 5v 10%; v dd2 = 5.0v 10%) (tc = -55 c to +125 c for "c" screening and -40 c to +125 c for "w" screening) notes: * for devices procured with a total ionizing dose tolerance gu arantee, the post-irradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. all specifications va lid for radiation dose 1e5 rad(si) per mil-std-883, method 1019. 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested 3. output skew is defined as a comparison of any two output tr ansitions of the same type at th e saame temperature and voltage f or the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus high-to-low an d low-to-high versus low-to-high; similarly 1b1 through 1b8 are compared, 2a1 through 2a8 are compared, and 2b1 through 2b8 are compared. 4. differential output skew is defined as a comparison of any two outp ut transitions of opposite ty pes on the same type at the same temperature and voltage for the same port within the same byte: 1a1 through 1a8 are compared high-t o-low versus low-to-high; simila rly 1b1 through 1b8 are compared , 2a1 through 2a8 are compared, and 2b1 through 2b8 are compared. symbol parameter min max unit ut54acs164245sei t plh propagation delay data to bus 3.5 9 ns t phl propagation delay data to bus 3.5 9 ns t pzl output enable time oe x to bus 3 9 ns t pzh output enable time oe x to bus 3 9 ns t plz output disable time oe x to bus high impedance 3 9 ns t phz output disable time oe x to bus high impedance 3 9 ns t pzl 2 output enable time dirx to bus 1 12 ns t pzh 2 output enable time dirx to bus 1 12 ns t plz 2 output disable time dirx to bus high impedance 1 15 ns t phz 2 output disable time dirx to bus high impedance 1 15 ns t skew 3 skew between outputs - 600 ps t dskew 4 differential skew between outputs - 1.5 ns
11 t plz t pzh t pzl t phz control input 5v output normally low enable disable times 5v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8v dd .2v dd v dd /2+0.2 v dd /2-0.2 .2v dd + .2v .8v dd - .2v t phl propagation delay input output v dd v dd /2 0v t plh v oh v ol v dd /2 t plz t pzh t pzl t phl t phz propagation delay input output v dd v dd /2 0v t plh v oh v ol v dd /2 control input 3.3v output normally low enable disable times 3.3v output normally high v dd v dd /2 0v v dd /2 v dd /2 .7v dd .2v dd v dd /2+0.2 v dd /2-0.2 .2v dd + .2v .7v dd - .2v
12 ac electrical characteristics* 1 (port a = port b, 3.3 volt operation) (v dd1 = 3.3v + 0.3v; v dd2 = 3.3v + 0.3v) (tc = -55 c to +125 c for "c" screening and -40 c to +125 c for "w" screening) notes: * for devices procured with a total ionizi ng dose tolerance guarantee, the post-irr adiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the ma ximum tid level procured. 1. all specifications valid for radiation dose 1e5 rad(si) per mil-std-883, method 1019 . 2. dirx to bus times are guarant eed by design, but not tested. oe x to bus times are tested. 3. output skew is defined as a comparison of any two output tran sitions of the same type at th e saame temperature and voltage f or the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus high-to-low an d low-to-high versus low-to-high; similarly 1b1 through 1b8 are compared, 2a1 through 2a8 are compared, and 2b1 th rough 2b8 are compared. 4. differential output skew is defined as a comparison of any two output transitions of opposite type s on the same type at the same temperature and voltage for the same port within the same byte: 1a1 thro ugh 1a8 are compared high-to-low versus low-to-high; similarly 1b1 through 1b8 are com pared, 2a1 through 2a8 are compared, and 2b1 through 2b8 are compared. symbol parameter min max unit ut54acs164245sei t plh propagation delay data to bus 3.5 11 ns t phl propagation delay data to bus 3.5 11 ns t pzl output enable time oe x to bus 2.5 16 ns t pzh output enable time oe x to bus 2.5 16 ns t plz output disable time oe x to bus high impedance 2.5 16 ns t phz output disable time oe x to bus high impedance 2.5 16 ns t pzl 2 output enable time dirx to bus 1 18 ns t pzh 2 output enable time dirx to bus 1 18 ns t plz 2 output disable time dirx to bus high impedance 1 20 ns t phz 2 output disable time dirx to bus high impedance 1 20 ns t skew 3 skew between outputs 600 ps t dskew 4 differential skew between outputs 1.5 ns
13 package figure 1. 48-lead flatpack 1. all exposed metalized areas are gold plated over electropl ated nickel per mil-prf-38535. 2. the lid is electrica lly connected to vss. 3. lead finishes are in a ccordance with mil-prf-38535. 4. lead position and colana rity are not measured. 5. id mark symbol is vendor option. 6. with solder, increase maximum by 0.003. 6 4 5 6
14 ordering information ut54acs164245sei: smd lead finish: (c) = gold case outline: (x) = 48 lead bb fp (gold only) class designator: (q) = class q (v) = class v device type (06) = 16-bit multipurpose transceiver with warm and cold spar ing (full mil-temp) (07) = 16-bit multipurpose tr ansceiver with warm and cold sp aring (extended industrial temp) drawing number: 98580 total dose: (note 1) (r) = 1e5 rad(si) federal stock class designator: no options 5962 r 98580 ** * * * notes: 1. total dose radiation must be specified when ordering . qml q and qml v not available without radiation hardening.
15 ut54acs164245sei ut54 *** ****** -* * * lead finish: (c) = gold screening: (c) = hirel temp (-55 o c to +125 o c) (p) = prototype (room temp only) (w) = extended industrial temp (-40 o c to +125 o c) package type: (u) = 48-lead bb fp (gold only) part number: (164245sei) = 16-bit multipur pose transceiver with warm and cold sparing i/o type: (acs)= cmos compatible i/o level aeroflex core part number notes: 1. hirel temperature range flow per aeroflex manufacturing flows document. devices are tested -55c, room temp, and 125c. radiati on neither tested nor guaranteed. 2. extended industrial temperature range flow per aeroflex manufacturing flows document. devices are tested at -40 o c, room temp, and +125 o c. radiation is neither tested nor guaranteed. 3. extended industrial range flow per aeroflex colorado sp rings manufacturing flows document . devices are tested at -40 c, room temp, and 125 c. radiation neither tested nor guaranteed.
16 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc. reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel

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